PCI2060 datasheet(16/76 Pages) TI

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Introduction

April 2005

SCPS096A

Table 2−4. PCI Primary Bus Address and Data Terminals

TERMINAL

NAME

GHK

NUMBER

I/O

DESCRIPTION

P_AD31

P_AD30

P_AD29

P_AD28

P_AD27

P_AD26

P_AD25

P_AD24

P_AD23

P_AD22

P_AD21

P_AD20

P_AD19

P_AD18

P_AD17

P_AD16

P_AD15

P_AD14

P_AD13

P_AD12

P_AD11

P_AD10

P_AD9

P_AD8

P_AD7

P_AD6

P_AD5

P_AD4

P_AD3

P_AD2

P_AD1

P_AD0

V10

U10

W14

R13

U14

P14

V15

U15

R17

N14

P17

P18

P19

M14

N18

N19

M17

M18

I/O

Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the

primary interface. During the address phase of a primary bus PCI cycle, P_AD31 through P_AD0 contain

a 32-bit address or other destination information. During the data phase, P_AD31 through P_AD0 contain

data.

P_C/BE3

P_C/BE2

P_C/BE1

P_C/BE0

P10

P13

R18

I/O

Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.

During the address phase of a primary bus PCI cycle, P_C/BE3 through P_C/BE0 define the bus

command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines

which byte paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7

through P_AD0), P_C/BE1 applies to byte 1 (P_AD15 through P_AD8), P_C/BE2 applies to byte 2

(P_AD23 through P_AD16), and P_C/BE3 applies to byte 3 (P_AD31 through P_AD24).

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