PCI2060 datasheet(21/76 Pages) TI

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Introduction

April 2005

SCPS096A

Table 2−9. Miscellaneous Terminals

TERMINAL

NAME

GHK

NUMBER

I/O

DESCRIPTION

BPCCE

Bus/power clock-control management terminal. When the BPCCE signal is tied high and when

the PCI2060 bridge is placed in the D3 power state, it enables the PCI2060 bridge to place the

secondary bus in the B2 power state. The PCI2060 bridge disables the secondary clocks and

drives them to 0. When tied low, placing the PCI2060 bridge in the D3 power state has no effect

on the secondary bus clocks.

GPIO3/ HSSWITCH

GPIO2

GPIO1

GPIO0

I/O

General-purpose I/O terminals

GPIO3 is HSSWITCH in the compactPCI mode.

HSSWITCH provides the status of the ejector handle switch to the compactPCI logic.

HSENUM

L15

Hot-swap ENUM. This signal notifies the host that a card insertion or removal event is pending.

HSLED

L14

Hot-swap LED output

MS0

E17

Mode select 0

MS1

T19

Mode select 1

P_M66ENA

W16

Primary interface 66-MHz enable. This input-only signal terminal designates the primary

interface bus speed. This signal must be pulled low for 33-MHz operation on the primary bus. In

this case, the S_M66ENA signal is driven low by the PCI2060 bridge, forcing the secondary bus

to run at 33 MHz. For 66-MHz operation, this signal must be pulled high.

CONFIG66

L18

Configure 66-MHz operation. This input-only terminal specifies whether the PCI2060 bridge is

capable of running at 66 MHz. If this terminal is tied high, then the device can be run at 66 MHz.

If this terminal is tied low, then the PCI2060 bridge can only function under the 33-MHz PCI

specification.

S_M66ENA

E18

I/O

Secondary 66-MHz enable. This signal designates the secondary bus speed. See Section 3.10.1

for more detail on the use of the S_M66ENA signal. Note that S_M66ENA is an open-drained

output.

SEC_ASYNC_CLK

Secondary asynchronous clock. This terminal is the secondary clock input when the

SEC_ASYNC_SEL terminal is high.

SEC_ASYNC_SEL

Secondary clock select. This terminal selects the clock that generates the secondary bus clock.

If SEC_ASYNC_SEL is low, then the primary PCI clock (P_CLK) input generates the secondary

bus clock. If SEC_ASYNC_SEL is high, then the SEC_ASYNC_CLK generates the secondary

bus clock.

SEC_ASYNC_RATE

D18

Secondary clock rate. This terminal selects the clock speed of the secondary bus clock. If

SEC_ASYNC_RATE is low, then the secondary clock outputs are one-half of the input clock

frequency. If SEC_ASYNC_RATE is high, then the secondary clock outputs are the same as the

input clock frequency.

MASK_IN

L17

Secondary clock disable serial input. This input-only signal is used by the hardware mechanism

to disable secondary clock outputs. The serial stream is received by the MASK_IN, starting

when P_RST is detected as deasserted and S_RST is detected as asserted. This serial data is

used for selectively disabling the secondary clock outputs and is shifted into the secondary clock

control register (offset 68h). This input can be tied low to enable all secondary clock outputs or

tied high to drive all secondary clock outputs high.

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