3

ATF2500C Family

0777I–PLD–4/03

Power-up Reset

The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed

slightly from V

depend on the polarity of the output buffer.

This feature is critical for state as nature of reset and the uncertainty of how V

in the system, the following conditions are required:

1.

2.

After reset occurs, all input and feedback setup times must be met before driving the

clock pin or terms high, and

3.

The clock pin, and any signals from which clock terms are derived, must remain stable

Parameter

Description

Typ

Max

Units

Power-up Reset Time

600

1000

ns

Power-up Reset Voltage

3.8

4.5

V

Level Forced on

Odd I/O Pin during

PRELOAD Cycle

Q Select Pin

State

Even/Odd

Select

Even Q1 State

after Cycle

Even Q2 State

after Cycle

Odd Q1 State

after Cycle

Odd Q2 State

after Cycle

Low

Low

High/Low

X

X

X

High

Low

X

High/Low

X

X

V

Low

High

X

X

High/Low

X

V

High

High

X

X

X

High/Low