4

ATF2500C Family

0777I–PLD–4/03

Preload and

Observability of

Registered

Outputs

The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-

chronously with either a high or a low. This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A V

appropriate register high; a V

tion bit settings.

The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When

the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12

registers chosen by the Q select and even/odd select pins.

Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.

In this mode, the contents of the buried register bank will appear on the associated outputs

when the OE control signals are active.

Programming

Software

Support

Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset

(no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this

case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The

ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the

lack of extra grounds on P4 and P26.

Security Fuse

Usage

A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once

programmed, the outputs will read programmed during verify.

The security fuse should be programmed last, as its effect is immediate.

The security fuse also inhibits Preload and Q2 observability.

Bus-friendly

Pin-keeper

Input and I/O

All ATF2500C family members have programmable internal input and I/O pin-keeper circuits.

The default condition, including when using the AT2500C/CQ family to replace the

AT2500B/BQ or AT2500H, is that the pin-keepers are not activated.

When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last

driven state. This ensures that all logic array inputs and device outputs are known states. Pin-

keepers are relatively weak active circuits that can be easily overridden by TTL-compatible

drivers (see input and I/O diagrams below).

Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the

logic compiler device selection menu. Please refer to the Software Compiler Mode Selection

table for more details. Once the pin-keeper circuits are disabled, normal termination proce-

dures required for unused inputs and I/Os.