FEDL7005-01

ML7005

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Status Register STR

D3

D2

D1

D0

SPB

FXDR

CPDR

DETF

Bit No.

Name

Description

D3

SPB

This bit is used to indicate whether the DTMF receive signal is being received.

"0" : Indicates that the valid DTMF signal is being received.

"1" : Indicates that the DTMF signal is not being received.

D2

FXDR

This bit is used to indicate whether the FAX signal (FX) is being received.

"0" : Indicates that the FAX signal (FX) is not being received.

"1" : Indicates that the valid FAX signal (FX: 1300 Hz) is being received.

When a call progress tone is received (CPDO="1"), this bit is forced to be "0".

When the DOEN register is "0", this bit also is fixed at "0". This bit has the same

unction as that of the FXDO.

D1

CPDR

This bit is used to indicate whether the call progress tone is being received.

"0" : Indicates that the call progress tone is not being received.

"1" : Indicates that the valid call progress tone (400 Hz) is being received.

When the DOEN register is "0", this bit is fixed at "0". This bit has the same function as

that of the CPDO pin.

D0

DETF

This is a flag to indicate that a detector has changed its status from a non-detect state to

a detect state.

This bit is "1" when:

(1) SPB is changed from "1" to "0",

(2) FXDR is changed from "0" to "1", or

(3) CPDR is changed from "0" to "1".

This bit remains "0" even if a 1300 Hz or 400 Hz signal is input, because the FXDR

and CPDR are fixed at "0" when the DOEN regsiter is "0".

When the processor has read the status register, this bit is reset to "0".

When the processor does not read the status register after a signal is detected, this bit is

"0" after the detected signal disappears.