ML9472 datasheet(5/18 Pages) ETC2

5 / 18 page

FEDL9472-02

LAPIS Semiconductor

ML9472

5/18

Symbol

Type

Description

COM_A

COM_B

LCD driving common signals is output from these pins.

These pins should be

connected to the COMMON side of the LCD panel.

- In the static display mode

A pulse in phase with the COM_OUT is output from both COM_A and COM_B. In

this case, the high level is VDD, and the low level is VLC2.

- In the 1/2 duty dynamic display mode

The COM_A and COM_B output signals are alternately changed within each

COM_OUT output cycle, resulting in alternate repetition of select and non-select

modes.

SEG1 to

SEG60

Display output pins for LCD. Theses pins are connected to the SEGMENT side of the

LCD panel. For the correspondence between the output of these pins and input data,

see Section, “Data Structure”.

VLC1, VLC2

—

Bias pins for LCD driver. Through these pins, bias voltages for the LCD are externally

supplied.

In the static display mode, VLC1 should be open.

VLC1 = VDD /2

VDD > VLC1 > VLC2 = GND

VDD, GND

—

Supply voltage pin and ground pin.

Note: Built-in schmitt circuit is used for all input pins.

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