CS22250 datasheet(29/32 Pages) CIRRUS

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CS22250 Wireless 10BT Controller

29 of 32

DS551PP2

Rev. 3.0

www.cirrus.com

Table 8. ROM/Flash Memory Read Timing

Item

Symbol

Min

Max

Clock Period

(1)

tperSMCLK

72 MHz

103 MHz

CE to SMD Latched Data

(2)

tid SMD

221 ns

OE de-asserted to OE asserted

(3)

tf SMRAS

6(tperSMCLK)

ROM address to output delay

(4)

tACC

220 ns

SMCLK to SMA output delay

td SMA

4.0 ns

SMCLK to BRCE output delay (CE)

td BRCE

4.5 ns

SMCLK to SMRAS output delay (OE)

td SMRAS

5.0 ns

SMD setup to SMCLK

tsu SMD

1.0 ns

SMD hold from SMCLK

th SMD

2.4 ns

1. The memclock timing is derived by bootstrap PLL settings. Synchronous modes at 77

MHz & 72 MHz are currently supported.

2. tid SMD is based on the fm_romrdlat register settings – default is 09h max. (77Mhz ~ 17

times SMCLK = 221ns).

3. tf SMRAS is the minimum time required before the next OE is active on the bus (6 times

SMCLK). The ROM device must release the bus within this time frame (77MHz ~ 78 ns).

4. Based on default fm_romrdlat register settings (note: 09h translates to 11h) see

fm_romrdlat register settings for more information.

SMCLK

SMD[7:0]

SMA[11:0], SMD[13:8]

SMNWE

BRCE (CE)

SMRAS (OE)

DATA

ADDRESS

tper

SMCLK

SMRAS

tld

SMD

BRCE

SMRAS

BRCE

tACC

SMA

tsu

SMD

t h

SMD

t f

SMRAS

Figure 7. ROM Memory Interface 'Read' Timing Diagram

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