CS4215 datasheet(13/52 Pages) CIRRUS

13 / 52 page

lected. SCLK and FSYNC must be synchronous

to the external clock.

As a third alternative, SCLK may be pro-

grammed to be the master clock input. In this

case, it must be 256 times Fs.

Serial Interface

The serial interface of the CS4215 transfers digi-

tal audio data and control data into and out of

the device. Multiple CS4215 devices may share

the same data lines. DSP’s supported include the

Motorola 56001 in network mode and a subset

of the ‘CHI’ bus from AT&T/Intel.

Serial Interface Signals

Figure 7 shows an example of two CS4215 de-

vices connected to a common controller. The

Serial Data Out (SDOUT) and Serial Data In

(SDIN) lines are time division multiplexed be-

tween the CS4215s.

The serial interface clock, SCLK, is used for

transmitting and receiving data. SCLK can be

generated by one of the CS4215s, or it can be

input from an external SCLK source. When gen-

erated by an external source, SCLK must be

synchronous to the master clock. Data is trans-

mitted on the rising edge of SCLK and is

received on the falling edge of SCLK. The

SCLK frequency is always equal to the bit rate.

The Frame Synchronizing signal (FSYNC) is

used to indicate the start of a frame. It may be

output from one of the CS4215s, or it may be

generated from an external controller. If FSYNC

is generated externally, it must be high for at

least 1 SCLK period, and it must fall at least

2 SCLKs before the start of a new frame (see

Figure 8). It must also be synchronous to the

master clock. The frequency of FSYNC is equal

to the system sample rate (see Figure 8). Each

CS4215 requires 64 SCLKs to transfer all the

data. The SCLK frequency can be set to 64, 128,

or 256 bits per frame, thereby allowing for 1, 2

or 4 CS4215s connected to the same bus.

In a typical multi-part scenario, one CS4215 (the

master) would generate FSYNC and SCLK,

while the other CS4215s (the slaves) would re-

ceive FSYNC and SCLK. The CLKOUT of the

master would be connected to the CLKIN of

each slave device as shown in Figure 7. Then,

the master device would be programmed for the

desired sample frequency (assuming one of the

crystals is selected as the clock source), the num-

ber of bits per frame, and for SCLK and FSYNC

to be outputs. The slave devices would be pro-

grammed to use CLKIN as the clock source, the

same number of bits per frame, and for SCLK

and FSYNC to be inputs. Since CLKOUT is al-

Controller

SCLK

SDIN

SDOUT

FSYNC

SCLK

SDIN

SDOUT

FSYNC

TSIN

TSOUT

PDN

RESET

CS4215

D/C

SCLK

SDIN

SDOUT

FSYNC

TSIN

TSOUT

PDN

RESET

CS4215

D/C

Master

Slave

CLKIN

CLKOUT

XTL1IN

XTL1OUT

XTL2IN

XTL2OUT

Figure 7. Multiple CS4215’s

CS4215

DS76F2

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