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CS43122 Datasheet(PDF) 19 Page - Cirrus Logic |
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CS43122 Datasheet(HTML) 19 Page - Cirrus Logic |
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19 / 28 page ![]() CS43122 19 5. APPLICATIONS 5.1 Recommended Power-up Sequence 1) Hold RST high until the power supplies, master clock, and left/right clock are stable. 2) Bring RST high. 6. CONTROL PORT INTERFACE The control port is used to load all the internal set- tings of the CS43122. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and “2 wire”, with the CS43122 operating as a slave device in both modes. If 2 wire operation is desired, AD0/CS should be tied to VD or DGND. If the CS43122 ever detects a high to low transition on AD0/CS af- ter power-up, SPI mode will be selected. 6.1 SPI Mode In SPI mode, CS is the CS43122 chip select signal, CCLK is the control port bit clock, CDIN is the in- put data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data is clocked on the rising edge of CCLK. Figure 5 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write in- dicator (R/W). The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data which will be placed into the register designated by the MAP. 6.2 2 Wire Mode In 2 Wire Mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 2. There is no CS pin. Pins AD0 and AD1 form the partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the first byte sent to the CS43122, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the op- eration is a read, then the contents of the register pointed to by the MAP will be output after the chip address. |
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