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occurrences of 8 consecutive zeros when B8ZS is enabled or 16 consecutive zeros when B8Z5 is

disabled. This counter increments at all times and is not disabled by a loss of sync condition (RLOS = 1).

The counter saturates at 65,535 and generates an interrupt for each occurrence after saturation if RIMR2.0

is set.

NOTE:

1. In order to properly preset the Bipolar Violation Count Register, BVCR2 must be written to before

BVCR1 is written to.

CRCCR: CRC COUNT REGISTER 2 Figure 5

MSB

LSB

CRC7

CRC6

CRC5

CRC4

CRC3

CRC2

CRC1

CRC0

SYMBOL

POSITION

NAME AND DESCRIPTION

CRC7

CRCCR.7

MSB of CRC6 word error count

CRC0

CRCCR.0

LSB of CRC6 word error count

The CRC Count Register (CRCCR) is an 8-bit presettable counter that records word errors in the Cyclic

Redundancy Check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each

occurrence after saturation if RIMR2.1 is set. The count in this register is only valid in the 193E framing

mode (RCR2.4 = 1) and is reset and disabled in the 193S framing mode (RCR2.4 = 0). The count is

disabled during a loss of sync condition (RLOS = 1).

OOFCR: OOF COUNT REGISTER Figure 6

MSB

LSB

OOF7

OOF6

OOF5

OOF4

OOF3

OOF2

OOF1

OOF0

SYMBOL

POSITION

NAME AND DESCRIPTION

OOF7

OOFCR.7

MSB of OOF event count

OFF0

OOFCR.0

LSB of OOF of event count

The OOF Count Register (OOFCR) is an 8-bit presettable counter that records Out Of Frame (OOF)

events.

OOF events are defined by RCR1.5 and RCR1.6. This 8-bit counter saturates at 255 and

generates an interrupt for each occurrence after saturation if RIMR2.2 is set. The count is disabled during

a loss of sync condition (RLOS = 1).