DS2182A

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RECEIVE STATUS REGISTERS

The receive status registers (RSR1 and RSR2) can be used in either a polled or an interrupt configuration.

In a polled configuration, the user reads the RSR at regular intervals to check for alarms. In an interrupt

occurred and has been reported in one of the RSRs. The processor can then read the RSRs to find which

bits have been set. All of the bits in the RSRs operate in a latched fashion. That is, once set, they remain

set until read. The bits in the RSR are cleared when read unless the read was performed in the burst mode

or the alarm condition still exists.

YELLOW ALARM

193S BIT 2. If RCR2.4 = 0 and RCR2.3 = 0, then the DS2182A examines bit 2 of all incoming channels

for the presence of a yellow alarm. If bit 2 is set to 0 in 256 consecutive channels, then the reception of a

yellow alarm is declared. The alarm is considered cleared when the first channel with bit 2 set to a 1 is

received.

193S S-BIT. If RCR2.4 = 0 and RCR2.3 = 1, then the DS2182A examines the S-bit position of frame 12

for the presence of a yellow alarm. The DS2182A declares the presence of a yellow alarm on the first

occurrence of the S-bit in frame 12 being set to 1. The alarm is considered cleared when this S-bit returns

to 0.

193E FDL. If RCR2.4 = 1, then the DS2182A examines the FDL for a repeating 00FF pattern. If this

pattern is received in the FDL 16 consecutive times without error, then a yellow alarm is declared. The

alarm is considered cleared as soon as any pattern other than 00FF is received.