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DS2182 Datasheet(PDF) 16 Page - Dallas Semiconductor |
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DS2182 Datasheet(HTML) 16 Page - Dallas Semiconductor |
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16 / 25 page ![]() DS2182A 16 of 25 193E RECEIVE MULTIFRAME TIMING Figure 15 NOTES: 1. Signaling data is updated during signaling frames on channel boundaries. Pin RABCD is the LSB of each channel word in non-signaling frames. 2. RLINK data (FDL data) is updated one bit-time prior to odd frames and held for two frames. RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16 NOTES: 1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held across multiframe edges. 2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods. |
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