DS5002FP datasheet(8/25 Pages) DALLAS

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DS5002FP Secure Microprocessor Chip

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AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING

(VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 6)

PARAMETER

SYMBOL

MIN

MAX

UNITS

Delay to Byte-Wide Address Valid from

CE1,

CE2, or CE1N Low During Op Code Fetch

tCE1LPA

Pulse Width of

CE1–4, PE1–4, or CE1N

tCEPW

4tCLK - 35

Byte-Wide Address Hold After

CE1, CE2, or

CE1N High During Op Code Fetch

tCE1HPA

2tCLK - 20

Byte-Wide Data Setup to

CE1, CE2, or CE1N

High During Op Code Fetch

tOVCE1H

1tCLK + 40

Byte-Wide Data Hold After

CE1, CE2, or CE1N

High During Op Code Fetch

tCE1HOV

Byte-Wide Address Hold After

CE1–4, PE1–4, or

CE1N High During MOVX

tCEHDA

4tCLK - 30

Delay from Byte-Wide Address Valid

CE1–4,

PE1–4, or CE1N Low During MOVX

tCELDA

4tCLK - 35

Byte-Wide Data Setup to

CE1–4, PE1–4, or

CE1N High During MOVX (Read)

tDACEH

1tCLK + 40

Byte-Wide Data Hold After

CE1–4, PE1–4, or

CE1N High During MOVX (Read)

tCEHDV

Byte-Wide Address Valid to R/

W Active During

MOVX (Write)

tAVRWL

3tCLK - 35

Delay from R/

W Low to Valid Data Out During

MOVX (Write)

tRWLDV

Valid Data Out Hold Time from

CE1–4, PE1–4, or

CE1N High

tCEHDV

1tCLK - 15

Valid Data Out Hold Time from R/

W High

tRWHDV

Write Pulse Width (R/

W Low Time)

tRWLPW

6tCLK - 20

Figure 6. Byte-Wide Bus Timing

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