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MA28140 Datasheet(PDF) 46 Page - Dynex Semiconductor

Part # MA28140
Description  Packet Telecommand Decoder
PDF  72 Pages
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Manufacturer  DYNEX [Dynex Semiconductor]
Direct Link  http://www.dynexsemi.com
Logo DYNEX - Dynex Semiconductor

MA28140 Datasheet(HTML) 46 Page - Dynex Semiconductor

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External Authentication Unit Interface
AUDIS
I
Internal AU disable signal. This signal allows bypassing of the internal or external authentication
unit. The internal and external AU are disabled when AUDIS is high. This signal can be
asynchronous
AUEXT
I
External AU select signal. This signal indicates the use of an external authentication unit. The
PTD uses the external AU when AUEXT is high and the internal AU when AUEXT is low. This
signal can be asynchronous
AUST
O
AU start signal. This signal indicates that a TC frame is received and must be authenticated.
It remains active as long as the external AU is working; it is deasserted after the activation of the
AUEND input. Active high.
AUBUF
O
Buffer indication signal. This signal indicates which back-end buffer contains the TC segment to
be authenticated.
AUBUF=0: buffer 0 is used
AUBUF=1: buffer 1 is used.
AUEND
I
AU result validation signal. This signal validates the authentication process result given on pin
AUR, and indicates the end of the authentication process. This signal can be asynchronous
AUR
I
AU result signal. This signal indicates that the received TC frame is authorized or not authorized.
AUR=0 indicates a bad authentication result, AUR=1 indicates a valid authentication. This signal
can be asynchronous.
AUTSL
I
AU tail length select signal. This signal indicates the length of the tail for segments authenticated
with the external AU.
- AUTSL = 0: the length of the AU tail is 9 octets
- AUTSL = 1: the length of the AU tail is 0 octets.
If the internal AU is selected (AUEXT = 0), this signal defines the implementation of the Recovery
LAC counter:
- AUTSL = 0: the Recovery LAC counter is stored outside the RAM
- AUTSL = 1: the Recovery LAC counter is stored in the RAM.
AUSBUF
O
AU Status buffer. This output indicates which AU status buffer that the external AU should update.
- AUSBUF = 0: AU status buffer 0
- AUSBUF = 1: AU status buffer 1.
FARBUF
O
FAR buffer. This output indicates which FAR status buffer that the external AU should update.
- FARBUF = 0: FAR status buffer 0
- FARBUF = 1: FAR status buffer 1.
Miscellaneous
RFAVN
I
Incoming signal from physical layer, used to generate CLCW report. Active low. Asynchronous.
VCLSB
I
Virtual Channel Identifier LSB (static input). This bit enables differentiation between nominal and
redundant decoder, even when using the same Configuration ROM for both decoders.
- VCLSB = 1: The ‘VC ID’ LSB read from the ROM is inverted
- VCLSB = 0: The ‘VC ID’ LSB read from the ROM is not inverted.
SELTC<2..0>
O
Selected TC channel signals. These outputs indicate the last selected TC channel on which the
data present in the back-end buffer was received, it does not concern the CLTUs being input.
SELTC<0> is the LSB.
DECOD
O
Decode state signal. This signal indicates that the PTD is in the Decode state (active for all bits
after the start sequence until and including the tail sequence); it can be used for a scrambler.
TMMOD
I
TM mode signal. This static signal allows selection of the telemetry serial mode.
- TMMOD = 0: the status (CPDUS, FAR, AUS) words are fetched with 5 samples
- TMMOD = 1: the status (CPDUS, FAR, AUS) words are fetched with 2 samples.
RESETN
I
Reset signal. This signal allows the initialization of the PTD. Active low.
PAR
I
Parallel or serial interface selecting pin. This static input allows selection of the parallel or serial
interface for MAP data and TM data.
- PAR = 1: parallel mode is selected
- PAR = 0: serial mode is selected.
MODE
I
Reserved pin. This static input shall be connected to ground.
CONF
I
Reserved pin. This static input shall be connected to ground.
PRIOR
I
Priority mode configuration pin. When this static input is set to 1, the priority mode (TC channels
selection) is selected.
TEST
I
Test pin for production test only. This static input shall be connected to ground in functional mode.
CLK
I
System Clock signal.
VDD
I
+5V (12 pins).
VSS
I
Ground (14 pins).



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