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LMH7322 Datasheet(PDF) 4 Page - Texas Instruments |
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LMH7322 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 33 page  LMH7322 SNOSAU8H – MARCH 2007 – REVISED MAY 2011 www.ti.com 12 AC Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TJ = 25°C, VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none.Boldface limits apply at temperature extremes. Min Typ Max Symbol Parameter Conditions Units (1) (2) (1) tjitter-RMS RMS Random Jitter Overdrive = ±100 mV; CL = 2 pF 702 fs Center Frequency = 140 MHz Bandwidth = 10 Hz–20 MHz tPDH Propagation Delay. Overdrive 20 mV 818 ps (see Figure 19 application note) Overdrive 50 mV 723 Input SR = Constant Overdrive 100 mV 708 ps VIN Startvalue = VREF −100 mV Overdrive 1V 703 tOD-disp Input Overdrive Dispersion tPDH @ Overdrive 20 mV ↔ 100 mV 110 ps tPDH @ Overdrive 100 mV ↔ 1V 5 tSR-disp Input Slew Rate Dispersion 0.1 V/ns to 1 V/ns; Overdrive = 100 48 ps mV tCM-disp Input Common Mode Dispersion SR = 1 V/ns; Overdrive = 100 mV; 43 ps 0V ≤ VCM ≤ VCCI- 1.5V ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 24 ps ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 45 ps tr Output Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 155 ps tf Output Fall Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 155 ps tsLE Latch Setup Time 77 ps thLE Latch Hold Time 33 ps tPD_LE Latch to Output Delay Time 944 ps 5V DC Electrical Characteristics Unless otherwise specified, all limits are specified for TJ = 25°C, VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ.Boldface limits apply at temperature extremes. Min Typ Max Symbol Parameter Conditions Units (1) (2) (1) INPUT CHARACTERISTICS IB Input Bias Current VIN Differential = 0V; RHYS = 8 kΩ −5 −2.6 µA Biased at VCM IOS Input Offset Current VIN Differential = 0V −250 40 +250 nA TC IOS Input Offset Current TC VIN Differential = 0V 0.3 nA/°C VOS Input Offset Voltage −8 −2 +8 mV TC VOS Input Offset Voltage TC 12 µV/°C VRI Input Voltage Range for CMRR ≥ 50 dB VEE−0.2 VCCI−1.5 V VRID Input Differential Voltage Range −1 +1 V CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ VCC1−0.2 80 dB PSRR Power Supply Rejection Ratio 80 dB AV Active Gain 53 dB Hyst Hysteresis VHYS = V(HYS+) -V(HYS-) , RHYS = 0Ω 25 50 75 mV LATCH ENABLE CHARACTERISTICS IB-LE Latch Enable Bias Current Biased at RSPECL Level 3 10 µA VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level +5 mV VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VEE+1.4 VCCO-0.8 V (1) All limits are specified by testing or statistical analysis. (2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. 4 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: LMH7322 |
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