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CLC021 Datasheet(PDF) 6 Page - Texas Instruments |
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CLC021 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 25 page  CLC021 SNLS068H – MAY 2000 – REVISED APRIL 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS—CLC021AVGZ-5.0 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter Conditions Reference Min Typ Max Units BRSDO Serial Data Rate See (2) SDO, SDO 100 400 Mbps Reference Clock FPCLK PCLK 10 40 MHz Input Frequency Reference Clock Duty PCLK 45 50 55 % Cycle tr, tf Rise Time, Fall Time DN, PCLK 1.0 1.5 3.0 ns tj Serial Output Jitter 270 Mbps (3), See Figure 3 220 psP-P tjit Serial Output Jitter See (2)(4) 100 200 psP-P SDO, SDO tr, tf Rise Time, Fall Time 20%–80% (2)(4) 500 800 1500 ps Output Overshoot See (4) 1 % tLOCK Lock Time See (2)(5) 75 µs tSU Setup Time See (4) and Figure 4 DN to PCLK 3 2 ns tHLD Hold Time See (4) and Figure 4 DN from PCLK 3 2 ns LGEN Output Inductance See (4) 6 nH SDO, SDO RGEN Output Resistance See (4) 25k Ω (1) Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25°C. (2) RL = 75Ω, AC-coupled @ 270 Mbps, RREF = 1.69 kΩ 1%, See TEST LOADS and Figure 3. (3) CLC021 mounted in the SD021EVK board, configured in BIST mode (NTSC colour bars) with PCLK = 27 MHz derived from Tektronix TG2000 black-burst reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window. (4) Specification is ensured by design. (5) Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true). AC ELECTRICAL CHARACTERISTICS—CLC021AVGZ-3.3 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter Conditions Reference Min Typ Max Units BRSDO Serial Data Rate See (2) SDO, SDO 100 400 Mbps Reference Clock FPCLK PCLK 10 40 MHz Input Frequency Reference Clock Duty PCLK 45 50 55 % Cycle tr, tf Rise Time, Fall Time DN, PCLK 1.0 1.5 3.0 ns tj Serial Output Jitter 270 Mbps (3), See Figure 3 220 psP-P tjit Serial Output Jitter See (2)(4) 100 200 psP-P SDO, SDO tr, tf Rise Time, Fall Time 20%–80% (2)(4) 500 800 1500 ps Output Overshoot See (4) 1 % tLOCK Lock Time See (2)(5) 75 µs tSU Setup Time See (4) and Figure 4 DN to PCLK 4 2 ns tHLD Hold Time See (4) and Figure 4 DN from PCLK 4 2 ns LGEN Output Inductance See (4) 6 nH SDO, SDO RGEN Output Resistance See (4) 25k Ω (1) Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25°C. (2) RL = 75Ω, AC-coupled @ 270 Mbps, RREF = 1.69 kΩ 1%, See TEST LOADS and Figure 3. (3) CLC021 mounted in the SD021EVK board, configured in BIST mode (NTSC colour bars) with PCLK = 27 MHz derived from Tektronix TG2000 black-burst reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window. (4) Specification is ensured by design. (5) Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true). 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 |
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