CLC021

SNLS068H – MAY 2000 – REVISED APRIL 2013

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BUILT-IN SELF-TEST (BIST)

The CLC021 has a built-in self-test (BIST) function. The BIST performs a comprehensive go/no-go test of the

device. The test uses either a full-field colour bar for NTSC or a PLL pathological for PAL as the test data

pattern. Data is input internally in the input data register, processed through the device and tested for errors. A

go/no-go indication is given at the Test_Output. Table 1 gives device pin functions and Table 2 gives the test

pattern codes used for this function. The signal level at Test_Output, pin 3, indicates a pass or fail condition.

The BIST is initiated by applying the code for the desired BIST to D0 through D3 (D9 through D4 are 00h) and a

those inputs D0 through D3 which require a logic-1 need be pulled high. After the Lock_Detect output goes high

indicating the VCO is locked on frequency, TPG_Enable, pin 29, is taken to a logic high. The Lock_Detect output

may be temporarily connected to TPG_Enable to automate BIST operation. Test_Output, pin 3, is monitored for

a pass/fail indication. If no errors have been detected, this output will go to a logic high level approximately 2 field

intervals after TPG_Enable is taken high. If errors have been detected in the internal circuitry of the CLC021,

Test_Output will remain low until the test is terminated. The BIST is terminated by taking TPG _Enable to a logic

low. Continuous serial data output is available during the test.

Figure 7. Built-In Self-Test Control Sequence

TEST PATTERN GENERATOR

The CLC021 includes an on-board test pattern generator (TPG). Four full-field component video test patterns

for both NTSC and PAL standards, and 4x3 and 16x9 raster sizes are produced. The test patterns are: flat-field

black, PLL pathological, equalizer (EQ) pathological and a modified 75%, 8-colour vertical bar pattern. The

pathologicals follow recommendations contained in SMPTE RP 178–1996 regarding the test data used. The

colour bar pattern does not incorporate bandwidth limiting coding in the chroma and luma data when transitioning

between the bars. For this reason, it may not be suitable for use as a visual test pattern or for input to video D-to-

A conversion devices unless measures are taken to restrict the production of out-of-band frequency components.

The TPG is operated by applying the code for the desired test pattern to D0 through D3 (D4 through D9 are

00h). Since all parallel data inputs are equipped with internal pull-down devices, only those inputs D0 through D3

which require a logic-1 need be pulled high. Next, apply a 27 MHz or 36 MHz signal, appropriate to the raster

frequency. Then, take TPG_Enable, pin 29, to a logic high. The serial test pattern data appears on the SDO

outputs. The Lock_Detect output may be temporarily connected to TPG_Enable to automate TPG operation. The

TPG mode is exited by taking TPG_Enable to a logic low. Table 1 gives device pin functions for this mode.

Table 2 gives the available test patterns and selection codes.

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