CLC021 datasheet(11/25 Pages) TI1

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VDDmin

VSS

0ns min

PCLK

10%

90%

10%

90%

RESET

VDD

VDDmin

VSS

10%

PCLK

VDD

30Ps min

CLC021

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SNLS068H – MAY 2000 – REVISED APRIL 2013

POWER-ON RESET AND RESET INPUT

The CLC021 has an internally controlled, automatic, power-on-reset circuit. Reset clears TRS detection

circuitry, all latches, registers, counters and polynomial generators, sets the EDH characters to 00h and disables

the serial output. The SDO outputs are tri-stated during power-on reset. The part will remain in the reset

condition until the parallel input clock is applied.

An active-HIGH-true, manual reset input is available at pin 1. It resets both the digital and PLL blocks. The reset

input has an internal pull-down device and is inactive when unconnected.

It is recommended that PCLK not be asserted until at least 30 µs after power has reached VDDmin. See Figure 5.

If manual reset is used during power-on, then PCLK may be asserted at any time as long as manual reset is not

de-asserted until VDDmin is reached. See Figure 6.

Figure 5. Power-On Reset Sequence

Figure 6. Power-On Reset Sequence with Manual Reset

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CLC021 Datasheet(PDF) 11 Page - Texas Instruments