P0071 datasheet(34/43 Pages) ALTERA

34 / 43 page

The input and output video interfaces on the tPad are configured and initialized by software running

on a Nios® II processor. Nios II software demonstrates how to control the clocked video input,

clocked video output, and mixer functions at run-time is also provided. The video system is

implemented using the SOPC Builder system level design tool. This abstracted design tool provides

an easy path to system integration of the video processing data path with a NTSC or PAL video

input, VGA output, Nios II processor for configuration and control. The Video and Image

Processing Suite MegaCore functions have common open Avalon-ST data interfaces and Avalon

Memory-Mapped (Avalon-MM) control interfaces to facilitate connection of a chain of video

functions and video system modeling. In addition, video data is transmitted between the Video and

Image Processing Suite functions using the Avalon-ST Video protocol, which facilitates building

run-time controllable systems and error recovery.

Figure 4-14 shows the Video and Image Processing block diagram.

Figure 4-14 VIP Camera Example SOPC Block Diagram (Key Components)

P0071 Datasheet(PDF) 34 Page - Altera Corporation