ADS42JB49 datasheet(34/73 Pages) TI1

34 / 73 page

PowerSupply

AVDD,DRVDD

RESET

SEN

ADS42JB49

ADS42JB69

SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013

www.ti.com

DEVICE CONFIGURATION

The ADS42JB49 and ADS42JB69 can be configured using a serial programming interface, as described in the

Serial Interface section. In addition, the device has four dedicated parallel pins (PDN_GBL, STBY, CTRL1, and

CTRL2) for controlling the power-down modes.

SERIAL INTERFACE

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data

output) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at

every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 16th

SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are

ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface functions

with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty

cycle.

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 78. Later during

operation, if required serial interface registers can be cleared by:

1. Either through a hardware reset or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 08h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on

the RESET pin.

Figure 78. Reset Timing Diagram

Table 3. Reset Timing (1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Delay from AVDD and DRVDD power-up to active RESET

Power-on delay

pulse

Reset pulse width

Active RESET signal pulse width

µs

Delay from RESET disable to SEN active

100

(1)

Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless

otherwise noted.

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