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ADS42JB49 Datasheet(PDF) 46 Page - Texas Instruments

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Part # ADS42JB49
Description  Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
PDF  73 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS42JB49 Datasheet(HTML) 46 Page - Texas Instruments

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ADS42JB49
ADS42JB69
SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013
www.ti.com
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
2B
SCRAMBLE EN
0
0
0
0
0
0
0
Default: 00h
D7
SCRAMBLE EN
Scramble enable bit in the JESD204B interface
0
Scrambling disabled
1
Scrambling enabled
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
OCTETS PER
2C
0
0
0
0
0
0
0
FRAME
Default: 00h
D[7:0]
OCTETS PER FRAME
Sets number of octets per frame (F)
0
10x mode using two lanes per ADC
1
20x mode using one lane per ADC
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
2D
0
0
0
FRAMES PER MULTIFRAME
Default: 00h
D[4:0]
FRAMES PER MULTIFRAME
Sets number of frames per multiframe
After reset, the default settings for frames per multiframe are:
10x
K = 16
20x
K = 8
For each mode, K should not be set to a lower value.
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
30
SUBCLASS
0
0
0
0
0
Default: 40h
D[7:5]
SUBCLASS
Sets JESD204B subclass. Note that the default value of these bits after reset is '010', which makes subclass 2
the default class.
000
Subclass 0
Backward compatibility with JESD204A
001
Subclass 1
Deterministic latency using SYSREF signal
010
Subclass 2
Deterministic latency using SYNC~ detection (default subclass after reset)
46
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42JB49 ADS42JB69



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