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ADS42JB49 Datasheet(PDF) 39 Page - Texas Instruments

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Part # ADS42JB49
Description  Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
PDF  73 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS42JB49 Datasheet(HTML) 39 Page - Texas Instruments

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ADS42JB49
ADS42JB69
www.ti.com
SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013
DESCRIPTION OF SERIAL INTERFACE REGISTERS
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
6
0
0
0
0
0
0
CLK DIV
Default: 00h
D[1:0]
CLK DIV
Internal clock divider for input sample clock
00
Divide-by-1 (clock divider bypassed)
01
Divide-by-2
10
Divide-by-1
11
Divide-by-4
REGISTER
REGISTER DATA
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
7
0
0
0
0
0
0
SYSREF DELAY
Default: 00h
Controls the delay of the SYSREF input with respect to the input clock. Typical
D[2:0]
SYSREF DELAY
values for the expected delay of different settings are:
000
0-ps delay
001
60-ps delay
010
120-ps delay
011
180-ps delay
100
240-ps delay
101
300-ps delay
110
360-ps delay
111
420-ps delay
Copyright © 2012–2013, Texas Instruments Incorporated
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Product Folder Links: ADS42JB49 ADS42JB69



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