ADS42JB49 datasheet(53/73 Pages) TI1

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CLKP

CLKM

0.1 F

CMOS

Clock Input

Device

0.1 F

ADS42JB49

ADS42JB69

www.ti.com

SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-

μF

capacitor, as shown in Figure 91. However, for best performance the clock inputs must be driven differentially,

thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using

a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.

There is no change in performance with a non-50% duty cycle clock input.

Figure 91. Single-Ended Clock Driving Circuit

DIGITAL GAIN

The device includes gain settings that can be used to obtain improved SFDR performance (compared to no

gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-

scale range scales proportionally. Table 10 shows how full-scale input voltage changes when digital gain are

programmed in 1-dB steps. Refer to Table 8 to set digital gain using a serial interface register.

SFDR improvement is achieved at the expense of SNR; for 1 dB increase in digital gain, SNR degrades

approximately between 0.5 dB and 1 dB. Therefore, gain can be used as a trade-off between SFDR and SNR.

Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage.

Table 10. Full-Scale Range Across Gains

DIGITAL GAIN

FULL-SCALE INPUT VOLTAGE

–2 dB

2.5 VPP

(1)

–1 dB

2.2 VPP

0 dB (default)

2.0 VPP

1 dB

1.8 VPP

2 dB

1.6 VPP

3 dB

1.4 VPP

4 dB

1.25 VPP

5 dB

1.1 VPP

6 dB

1.0 VPP

(1)

Shaded cells indicate performance settings used in the Electrical

Characteristics and Typical Characteristics.

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