ADS42JB49 datasheet(52/73 Pages) TI1

52 / 73 page

CLKP

1.4 V

5 kW

20 W

2 nH

PKG

1 pF

BOND

100 W

ESR

CLKM

Clock Buffer

20 W

2 nH

PKG

1 pF

BOND

100 W

ESR

CLKP

CLKM

0.1 F

Device

100 W

0.1 F

TypicalLVPECL

ClockInput

150 W

CLKP

CLKM

0.1 F

100 W

Device

0.1 F

TypicalLVDS

ClockInput

CLKP

CLKM

0.1 F

Device

0.1 F

Differential

Sine-Wave

ClockInput

ADS42JB49

ADS42JB69

SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013

www.ti.com

CLOCK INPUT

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V

using internal 5-k

Ω resistors. The self-bias clock inputs of the ADS42JB69 and ADS42JB49 can be driven by the

transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown

in Figure 87, Figure 88, and Figure 89. See Figure 90 for details regarding the internal clock buffer.

NOTE: RT = termination resistor, if necessary.

Figure 87. Differential Sine-Wave Clock Driving

Figure 88. LVDS Clock Driving Circuit

Circuit

Figure 89. LVPECL Clock Driving Circuit

NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 90. Internal Clock Buffer

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ADS42JB49 Datasheet(PDF) 52 Page - Texas Instruments

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