ADS42JB49 datasheet(49/73 Pages) TI1

49 / 73 page

INxP

(1)

INxM

RIN

ZIN

(2)

CIN

ADS42JB49

ADS42JB69

www.ti.com

SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS42JB69 and ADS42JB49 is a family of high linearity, buffered analog input, dual-channel ADCs with

maximum sampling rates up to 250 MSPS employing JESD204B interface. The conversion process is initiated by

a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is

sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction

logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 23

clock cycles. The output is available in CML logic levels following JESD204B standard.

ANALOG INPUT

The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential

sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external

driving source (10-k

Ω dc resistance and 4-pF input capacitance). The buffer helps isolate the external driving

source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier

than when compared to an ADC without the buffer.

The input common-mode is set internally using a 5-k

Ω resistor from each input pin to VCM so the input signal

can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and

VCM – 0.5 V, resulting in a 2-V PP differential input swing. When programmed for 2.5-V PP full-scale, each input

pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V.

The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-

Ω source

driving a 50-

Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the

maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to

approximately 400 MHz (with a 2-VPP full-scale amplitude). This 3-dB bandwidth is different than the analog

bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.

Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This technique improves the common-

mode noise immunity and even-order harmonic rejection. A small resistor (5

Ω to 10 Ω) in series with each input

pin is recommended to damp out ringing caused by package parasitics.

Figure 82, Figure 83, and Figure 84 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The

presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.

(1) X = A or B.

(2) ZIN = RIN || (1 / jωCIN).

Figure 82. ADC Equivalent Input Impedance

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