HT47C20 datasheet(17/56 Pages) HOLTEK

17 / 56 page

HT47C20

January 18, 2000

methods are adopted, external reset (a low level

to RES), software instruction, or a HALT instruc-

tion. The software instructions are of two types

which include CLR WDT and the other set - CLR

WDT1 and CLR WDT2. Of these two types of in-

struction, only one can be active depending on

the mask option -²CLR WDT times selection op-

tion².Ifthe ²CLR WDT² is selected (i.e., CLR

WDT times equal one), any execution of the CLR

WDT instruction will clear the WDT. In case ²CLR

WDT1² and ²CLR WDT2² are chosen (i.e. CLR

WDT times equal two), these two instructions

must be executed to clear the WDT; otherwise,

the WDT may reset the chip because of

time-out.

The WDT time-out period ranges from

fs/215~fs/216. Because the ²CLR WDT² or ²CLR

WDT1² and ²CLRWDT2² instruction only clear

the last two-stage of the WDT.

Multi-function timer

The HT47C20 provides a multi-function timer

for WDT, time base and real time clock but with

different time-out periods. The multi-function

timer consists of a 7-stage divider and an 8-bit

prescaler, with the clock source coming from

WDT OSC or RTC OSC or the instruction clock

(i.e., system clock divided by 4). The

multi-function timer also provides a selectable

frequency signal (ranges from fs/22 to fs/28) for

LCD driver circuits, and a selectable frequency

signal (ranges from fs/22 to fs/29) for buzzer out-

put by mask option. It is recommended to select

a near 4kHz signal for LCD driver circuits for

proper display.

Time base

The time base offers a periodic time-out period

to generate a regular internal interrupt. Its

time-out period ranges from fs/212 to fs/215 se-

lected by mask option. If time base time-out oc-

curs, the related interrupt request flag (TBF;

bit 5 of INTC0) is set. But if the interrupt is en-

abled, and the stack is not full, a subroutine call

to location 08H occurs.

When the HALT instruction is executed, the

time base still works (if WDT clock source co-

mes from WDT RC OSC or RTC OSC) and can

wake up from halt mode.

If the TBF is set ²1² before entering the halt

mode, the wake up function will be disable.

S yst e m C l o ck/ 4

D i v i der

Pr e s c a l e r

W D T C l ear

Ma s k

Op t i o n

Se l e c t i o n

WD T

OS C 12k H z

RT C

OS C 327 68H z

f s

CK T

T i m e - o ut R es et

f s /2

~ f s /2

f s /2

Watchdog timer

D i v i der

f s

Ma s k O p t i o n

Pr e s c a l e r

LC D D r i v er

T i m e B as e I n t e r r upt

f s /2

~ f s /2

Bu z z e r

f s /2 ~ f s /2

f s /2

Time base

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