HB7121B

Semiconductor Inc.

CMOS IMAGE SENSOR

System IC SBU

With 8-bit ADC

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. NO patent licenses are implied.

DA21000601R_1.1

- 4 -

2001 Hynix System IC SBU

INPUT / OUTPUT AC CHARACTERISTICS

l

All output timing delays are measured with output load 60[pF].

l

Output delay include the internal clock path delay 6[ns] and output driving delay that changes in

respect to the output load, the operating environment, and a board design.

l

Due to the variable valid time delay of the output, output signals may be latched in the negative

edge of MCLK for the stable data transfer between the image sensor and a host for less than

15MHz operation.

MCLK to HSYNC/VSYNC Timing

MCLK to DATA Timing

Note) HSYNC signal is high when valid data is on the DATA bus.

DATA[7:0]

valid data

MCLK

PCLK