80960JD datasheet(31/61 Pages) INTEL

31 / 61 page

PRELIMINARY

80960JD

RELATIVE OUTPUT TIMINGS

TLXL

ALE/ALE Width

0.5T

C - 7.5

(9)

LXA

Address Hold from ALE/ALE

Inactive

Equal Loading (9)

TDXD

DT/R Valid to DEN Active

Equal Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

BSF

TCK Frequency

0.5T

MHz

TBSCH

TCK High Time

Measured at 1.5 V (1)

TBSCL

TCK Low Time

Measured at 1.5 V (1)

BSCR

TCK Rise Time

0.8 V to 2.0 V (1)

TBSCF

TCK Fall Time

2.0 V to 0.8 V (1)

TBSIS1

Input Setup to TCK — TDI, TMS

BSIH1

Input Hold from TCK — TDI,

TMS

TBSOV1

TDO Valid Delay

(1,10)

TBSOF1

TDO Float Delay

(1,10)

BSOV2

All Outputs (Non-Test) Valid

Delay

(1,10)

TBSOF2

All Outputs (Non-Test) Float

Delay

(1,10)

TBSIS2

Input Setup to TCK — All Inputs

(Non-Test)

BSIH2

Input Hold from TCK — All

Inputs (Non-Test)

Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

Notes

NOTE:

See Table 16 on page 28 for note definitions for this table.

80960JD Datasheet(PDF) 31 Page - Intel Corporation

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