80960JD datasheet(33/61 Pages) INTEL

33 / 61 page

PRELIMINARY

80960JD

TOV2

Output Valid Delay, DT/R

0.5TC + 3.5

0.5TC + 18

TOF

Output Float Delay

3.5

(4)

SYNCHRONOUS INPUT TIMINGS

TIS1

Input Setup to CLKIN — AD31:0, NMI,

XINT7:0

(5)

TIH1

Input Hold from CLKIN — AD31:0, NMI,

XINT7:0

(5)

IS2

Input Setup to CLKIN — RDYRCV and

HOLD

(6)

TIH2

Input Hold from CLKIN — RDYRCV and

HOLD

(6)

TIS3

Input Setup to CLKIN — RESET

(7)

IH3

Input Hold from CLKIN — RESET

(7)

TIS4

Input Setup to RESET — ONCE, STEST

(8 )

TIH4

Input Hold from RESET — ONCE,

STEST

(8)

RELATIVE OUTPUT TIMINGS

TLXL

ALE/ALE Width

0.5TC - 7.5

(9)

TLXA

Address Hold from ALE/ALE Inactive

Equal

Loading (9)

DXD

DT/R Valid to DEN Active

Equal

Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

TBSF

TCK Frequency

0.5TF

MHz

BSCH

TCK High Time

Measured at

1.5 V (1)

TBSCL

TCK Low Time

Measured at

1.5 V (1)

TBSCR

TCK Rise Time

0.8 V to 2.0

V (1)

BSCF

TCK Fall Time

2.0 V to 0.8

V (1)

TBSIS1

Input Setup to TCK — TDI, TMS

TBSIH1

Input Hold from TCK — TDI, TMS

BSOV1

TDO Valid Delay

(1, 10)

TBSOF1

TDO Float Delay

(1, 10)

Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 2 of 3)

Symbol

Parameter

Min

Max

Units

Notes

80960JD Datasheet(PDF) 33 Page - Intel Corporation

80960JD Datasheet(HTML) 33 Page - Intel Corporation

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