82374EB datasheet(31/208 Pages) INTEL

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82374EB82374SB

2114 KEYBOARD CONTROLLER INTERFACE

Pin Name

Type

Description

KYBDCS

out

KEYBOARD CHIP SELECT

KYBDCS

is connected to the chip select of the 82C42

KYBDCS

is active for IO addresses 0060h and 0064h

ALTRST

out

ALTERNATE RESET

ALTRST

is used to reset the CPU under program control

This signal is AND’ed together externally with the reset signal (RSTAR ) from the

keyboard controller to provide a software means of resetting the CPU This provides a

faster means of reset than is provided by the Keyboard controller Writinga1tobit0in

the Port 92 register will cause this signal to pulse active (low) for approximately 4

BCLK’s Before another ALTRST

pulse can be generated bit 0 must be written back

to a 0 During reset this signal is driven low

ALTA20

out

ALTERNATE A20

ALTA20 is used to force A20M

to the CPU low for support of real

mode compatible software This signal is externally OR’ed with the ALTA20 signal

from the Keyboard controller and CPURST to control the A20M

input of the CPU

Writing a ‘‘0’’ to bit 1 of Port 92h Register will force ALTA20 inactive (low ) This in turn

will drive A20M

to the CPU low if A20GATE from the keyboard controller is also low

Writing a ‘‘1’’ to bit 1 of the Port 92h Register will force ALTA20 active (high) which in

turn will drive A20M

to the CPU high regardless of the state of ALTA20 from the

keyboard controller Upon reset this signal is driven low

ABFULL

AUXILIARY BUFFER FULL

ABFULL is tied directly to the ABFULL signal on the

keyboard controller on the system board This signal indicates that the keyboard

controller auxiliary buffer for the mouse interface is full See the CLKDIV Register

desciption for programming the ABFULL function If this function is not used ABFULL

should be tied low through a 1K resistor

2115 REAL TIME CLOCK INTERFACE

Pin Name

Type

Description

RTCALE

out

REAL TIME CLOCK ADDRESS LATCH ENABLE

RTCALE is directly connected to

the system Real Time Clock The RTC uses this signal to latch the appropriate memory

address A write to port 070h with the appropriate Real Time Clock memory address

that will be written to or read from will cause RTCALE to go active

RTCRD

out

REAL TIME CLOCK READ COMMANDPCI INTERRUPT REQUEST 3

This signal

pin has two functions and the function is selected via the Mode Select Register When

PIRQ3

functioning as RTCRD

this signal is asserted for IO reads from address 0071h If

the Power On Password protection is enabled (IO Port 92h bit 3e1) then for

accesses to RTC addresses 36h – 3Fh (Port 70h) RTCRD

will not be asserted For

details on PIRQ3

see the Mode Select Register description For the PIRQ3

function an external pull-up resistor (10-20 K) must be added to this signal

82374EB Datasheet(PDF) 31 Page - Intel Corporation

82374EB Datasheet(HTML) 31 Page - Intel Corporation

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