82374EB datasheet(41/208 Pages) INTEL

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82374EB82374SB

317 PCSAPERIPHERAL CHIP SELECT A REGISTER

Address Offset

4Eh

Default Value

x0000111b

Attribute

ReadWrite

Size

8 Bits

This register is used to enable or disable accesses to the RTC keyboard controller Floppy Disk controller and

IDE Disabling any of these bits will prevent the chip select and X-Bus transceiver control signal (XBUSOE )

for that device from being generated This register is also used to select which address range (primary or

secondary) will be decoded for the resident floppy controller and IDE It also allows control of where the

keyboard controller is physically located (X-Bus or elsewhere)This insures that there is no contention with the

X-Bus transceiver driving the system data bus during read accesses to these devices

Bit

Description

Reserved

Keyboard Controller Mapping

0ekeyboard controller mapped to the X-Bus (default)

1ekeyboard controller not mapped to the X-Bus

When bit 6e0 the keyboard controller encoded chip select signal and the X-Bus transceiver enable

(XBUSOE ) are generated for accesses to address locations 60h (82374EBSB) 62h (82374EB

only) 64h (82374EBSB) and 66h (82374EB only) When bit 6e1 the keyboard controller chip

select signals are generated for accesses to these address locations However XBUSOE

disabled Bit 1 must be 1 for either value of this configuration bit to decode an access to locations

60h 62h 64h or 66h

532

Floppy Disk and IDE Floppy Disk Decodes

Bits 2 and 3 are used to enable or disable the floppy

locations as indicated Bit 2 defaults to enabled (1) and bit 3 defaults to disabled (0) when a reset

occurs Bit 5 is used to select between the primary and secondary address range used by the Floppy

Controller and the IDE Only primary or only secondary can be programmed at any one time This bit

defaults to primary (0) The following table shows how these bits are used to select the floppy

controller

Address

Bit 2

Bit 3

Bit 5

DSKCHG

FDCCS

XXX0

3F0h3F1h

3F2h – 3F7h

0 (Note)

370h371h

372h – 37Fh

0 (Note)

NOTE

If IDE decode is enabled all accesses to locations 03F6h and 03F7h (primary) or 0376h and

0377h (secondary) will result in decode for IDECS1

(FDCCS

will not be generated) An

external AND gate can be used to tie IDECS1

and FDCCS

together to insure that the

floppy is enabled for these accesses

82374EB Datasheet(PDF) 41 Page - Intel Corporation

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