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82374EB Datasheet(PDF) 36 Page - Intel Corporation |
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82374EB Datasheet(HTML) 36 Page - Intel Corporation |
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36 / 208 page  82374EB82374SB 311 ESCIDESC ID REGISTER Address Offset 02h Default Value 00h Attribute ReadWrite Size 8 Bits Since the ESC configuration registers are accessed by the index addressing mechanism using IO Ports 22h and 23h it is possible that another device in the system might use the same approach for configuration In order to avoid contention with similar index register devices the ID register must be written with 0Fh The ESC will not respond to accesses to any other configuration register until the ID byte has been written in the ESC ID Register Bit Description 70 ESC ID Byte These bits must be written to a value of 0Fh before the ESC will respond to any other configuration register access After a reset has occurred all of the configuration registers except this register are disabled 312 RIDREVISION ID REGISTER Address Offset 08h Default Value 02h (82374EB A-2 stepping) 03h (82374SB B-0 stepping) Attribute Read only Size 8 Bits This 8-bit register contains device stepping information Writes to this register have no effect Bit Description 70 Revision ID Byte These bits contain the stepping information about the device The register is hardwired to the default value during manufacturing The register is read only Writes have no effect on the register value 313 MSMODE SELECT REGISTER Address Offset 40h Default Value 20h Attribute ReadWrite Size 8 Bits This register selects the various functional modes of the ESC Bit Description 7 Reserved 6 MREQ 74 PIRQ 30 Enable This bit enables the selected (MREQ 74 PIRQ 30 functionality 1eEnabled 0eDisabled 5 Configuration RAM Address This bit is used to enable or disable the configuration RAM Page Address (CPG 40 ) generation If this bit is set to 1 accesses to the configuration RAM space will generate the RAM page address on the LA 3127 pins If this bit is set to 0 the CPG 40 signals will not be activated The default for this bit is 1 36 |
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