82374EB datasheet(34/208 Pages) INTEL

34 / 208 page

82374EB82374SB

Pin Name

Type

Description

XBUSOE

out

X-BUS DATA OUTPUT ENABLE

XBUSOE

is tied directly to the output enable of

a 74F245 that buffers the X-Bus data XD(70) from the system data bus SD(70)

For EISA and ISA master memory read or write cycles XBUSOE

is asserted

when LBIOSCS

is asserted Otherwise XBUSOE

is not asserted

For EISA and ISA master IO read or write cycles SBUSOE

is asserted if an ISC

supported X-Bus device has been decoded and the decoding for that device has

been enabled via the proper configuration registers An exception to this is during

an IO read access to floppy location 3F7h (primary) or 377h (secondary) if the IDE

decode space is disabled (ie IDE is not present on the X-Bus) In this case

XBUSOE

is not asserted XBUSOE

is also not asserted during an IO access to

the floppy controller if DSKCHG is sampled low at reset

XBUSOE

is not asserted during DMA cycles except for channel 2 DMA For

channel 2 DMA XBUSOE

is asserted

GPCS 20

out

GENERAL PURPOSE CHIP SELECTENCODED CHIP SELECT

These are dual

function signals The function of these pins is selected through the Mode Select

ECS 20

General Purpose Chip Select

GPCS 20

are chip selects for peripheral

devices The peripheral devices can be mapped in the IO range by programming

the General Purpose Chip Select Base Address registers and General Purpose

Mask registers (offset 64h-6Eh)

Encoded Chip Select

ECS 20 provide encoded chip select decoding for serial

ports parallel port IDE and general purpose devices The device chip selects for

the peripheral devices are generated by using a F138 with ECS 20 as inputs

Hardware Reset (Test Mode)

82374SB

During Reset GPCS0ECS0 is an input signal The level of this signal is sampled at

the end of the reset sequence to determine whether the TEST pin is used as the

current TEST function (sampled ‘‘1’’) or as the INIT signal (sampled ‘‘0’’) After

reset the existing GPCSECS functionality on this pin is maintained Note that an

internal pull-up of approximately 8 KX is included on this pin If the INIT mode on

the TEST pin is to be selected an external pull-down of approximately 500X should

be connected to the pin

82374EB Datasheet(PDF) 34 Page - Intel Corporation

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