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changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

November 1995

COPYRIGHT

INTEL CORPORATION 1995

Order Number 270999-007

87C196KT87C196KS

ADVANCED 16-BIT CHMOS MICROCONTROLLER

Automotive

Y

High Performance CHMOS 16-Bit CPU

Y

Up to 32 Kbytes of On-Chip EPROM

Y

Up to 1 Kbyte of On-Chip Register RAM

Y

Up to 512 Bytes of Additional RAM

(Code RAM)

Y

Register-Register Architecture

Y

8 Channel10-Bit AD with SampleHold

Y

37 Prioritized Interrupt Sources

Y

Up to Seven 8-Bit (56) IO Ports

Y

Full Duplex Serial IO Port

Y

Dedicated Baud Rate Generator

Y

Interprocessor Communication Slave

Port

Y

Selectable Bus Timing Modes for

Flexible Interfacing

Y

Oscillator Fail Detection Circuitry

Y

High Speed Peripheral Transaction

Server (PTS)

Y

Two Dedicated 16-Bit High-Speed

Compare Registers

Y

10 High Speed CaptureCompare (EPA)

Y

Full Duplex Synchronous Serial IO

Port (SSIO)

Y

Two Flexible 16-Bit TimerCounters

Y

Quadrature Counting Inputs

Y

Flexible 8-16-Bit External Bus

(Programmable)

Y

Programmable Bus (HLDHLDA)

Y

175 ms 16 x 16 Multiply

Y

3 ms 3216 Divide

Y

68-Pin PLCC Package

The 87C196Kx devices represents the 4th generation of MCS

96 microcontroller products implemented on

Intel’s advanced 1 micron process technology These products are based on the 80C196KB device with

enhancements ideal for automotive applications The instruction set is a true super set of the 80C196KB with a

few new instructions

The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The

87C196KT is composed of the high speed (16 MHz) KX macrocore as well as the following peripherals Up to

32 Kbytes of Program EPROM up to 1 Kbytes of Register RAM (00-3FFH including SFRs) up to 512 bytes of

code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10 Bit

g

asynchronoussynchronous serial IO port (8096 compatable) with a dedicated 16-bit baud rate generator an

additional synchronous serial IO port with full duplex masterslave transceivers a flexible timercounter

structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed IO

for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs

and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) The

PTS has several channel modes including singleburst block transfers from any memory location to any

memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an AD scan

mode

Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area

NOTICE

This datasheet contains information on products in production The specifications are subject to change

without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a

design

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