87C196 datasheet(32/34 Pages) INTEL

32 / 34 page

87C196KT87C196KS

87C196KTKS ERRATA

The following is a list of all known functional devia-

tions for 87C196KTKS devices B-step and later

devices can be identified by a special mark following

the eight digit FPO number on the top of the pack-

age For C-step devices this mark is a ‘‘C’’

1 HOLD OR READY DURING DIVIDE (A-step)

There is a bug in the DIV and DIVB (signed di-

vide) instructions such that if the following 2 con-

ditions are met there may be an error of 1 in the

quotient

a) HOLD or READY is asserted during the first

state of execution of the DIV and DIVB in-

struction

b) HOLD or READY duration is 16 state times for

the DIVB or 24 state times for a DIV instruc-

tion

2 P27 (CLKOUT) (A-step)

Port 27 (CLKOUT) does not operate in open

drain mode

3 P2

REG7 AND P6

REG4 THROUGH P6

REG7 CLEARED (A-step)

REG7 is cleared when P2

SSEL7 bit is

changed froma1toa0 (special function to

LSIO) P6

Reg4 – 7 is cleared when the corre-

sponding P6

SSEL4 – 7 is changed froma1to

4 INDIRECT SHIFT INSTRUCTION (A-step)

The upper three bits of the byte register holding

the shift count are not masked completely If the

shift count register has the value 32 x n where n

1 3 5 or 7 the operand wil be shifted 32

times The above condition results in NO shift

taking place

5 INTERNAL RAM POWERDOWN LEAKAGE

(A-step)

If an invalid address is applied to the internal

RAM during power-down the address lines float

This can cause increased current consumption

during power-down To insure a valid address on

the internal RAM execute the idlepower-down

instruction from internal RAM

6 INST PIN (A-step)

On A-step devices the INST pin is pulled medium

low for approx 200 ns after RESET and then

pulled weakly

HIGH until P5SSEL is written to

This is corrected on B-step devices where the

INST pin is pulled medium low for approx 200 ns

after RESET and is then pulled weakly

LOW until

P5SSEL is written to

7 REGISTER

RAM

OVERWRITE

(A-step

B-step)

If a write is performed to a byteword location

within the SFR range of 1F60h to 1FFFh the

data to be written is also written to a correspond-

ding location located within the REGISTER RAM

space 360h to 3FFh To determine the address

of the REGISTER RAM location that is overwrit-

ten an offset of 1C00h can be subtracted from

the byteword addressed in the SFR range

8 BUS TIMING MODES 1 AND 2 (A-step B-step)

Bus timing modes 1 and 2 are not featured or

specified on A-step and B-step parts On C-step

parts Mode 1 is selected by setting bits MSEL1

0 and MSEL0 e 1 in the CCB1 register

Mode 2 is similarly selected by setting MSEL1 e

1 and MSEL0 e 0

Timings are altered by

Mode 1 and Mode 2 as follows (for actual values

see the Bus Mode 1 and Bus Mode 2 AC Charac-

teristics in this data sheet)

Mode 1 RD WR advanced 1 TOSC

ALE advanced 05 TOSC

ALE pulse width remains 1 TOSC

Mode 2 RD WR advanced 1 TOSC

ALE advanced 05 TOSC

ALE pulse width remains 1 TOSC

Address advanced 05 TOSC

9 VOH2 (A-step b-step)

A- and B-step parts are capable of VOH2 e VCC

1V with IOH eb6 mA C-step devices meet

the target values of VOH2 e VCC b 1V with IOH

15 mA

10 CLKOUT DURING RESET (A-step

B-step

C-step)

For

all

steppings

the

87C196KT

the

CLKOUT function during RESET (P27) differs

from the 87C196KR C-step During RESET on

the 87C196KT CLKOUT does not toggle and

remains in the high state During RESET on the

87C196KR C-step CLKOUT countinues to tog-

gle

87C196 Datasheet(PDF) 32 Page - Intel Corporation

87C196 Datasheet(HTML) 32 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL