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87C196 Datasheet(PDF) 6 Page - Intel Corporation |
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87C196 Datasheet(HTML) 6 Page - Intel Corporation |
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6 / 34 page ![]() 87C196KT87C196KS CCB (2018H Byte) 0PD e ‘‘1’’ Enables Powerdown 1 BW0 e See Table 2WR e ‘‘1’’ e WR BHE - ‘‘0’’ e WRL WRH 3 ALE e ‘‘1’’ e ALE - ‘‘0’’ e ADV 4 IRC0 e See Table 5 IRC1 e ( 6 LOC0 e See Table 7 LOC1 e ( CCB1 (201AH Byte) 00 e Reserved Must Be ‘‘0’’ 1 IRC2 e See Table 2 BW1 e See Table 3 WDE e ‘‘0’’ e Always Enabled 41 e Reserved Must Be ‘‘01’’ 50 e ( 6 MSEL0 e See Table 7 MSEL1 e ( LOC1 LOC0 Function 0 0 Read and Write Protected 0 1 Write Protected Only 1 0 Read Protected Only 1 1 No Protection IRC2 IRC1 IRC0 Max Wait States 0 0 0 Zero Wait States 1 0 0 1 Wait State 1 0 1 2 Wait States 1 1 0 3 Wait States 1 1 1 INFINITE MSEL1 MSEL0 Bus Timing Mode 0 0 Mode 0 (1-Wait KR) 0 1 Mode 1 1 0 Mode 2 1 1 Mode 3 (KR) BW1 BW0 Bus Width 0 0 ILLEGAL 0 1 16-Bit Only 1 0 8-Bit Only 1 1 BW Pin Controlled Mode 0 Designed to be similar to the 87C196KR bus (1-Wait KR) timing with 1 automatic wait state See AC Timings section for actual timings data Mode 1 RD WR advanced 1 TOSC ALE advanced 05 TOSC ALE pulse width remains 1 TOSC Mode 2 RD WR advanced 1 TOSC ALE advanced 05 TOSC ALE pulse width remains 1 TOSC Address advanced 05 TOSC Mode 3 (KR) Designed to be similar to the 87C196KR bus timing See AC Timings section for actual timings data 6 6 |
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