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87C196 Datasheet(PDF) 33 Page - Intel Corporation

Part # 87C196
Description  ADVANCED 16-BIT CHMOS MICROCONTROLLER
PDF  34 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

87C196 Datasheet(HTML) 33 Page - Intel Corporation

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87C196KT87C196KS
87C196KTKS DESIGN CONSIDERATIONS
1 EPA TIMER RESETWRITE CONFLICT
If the user writes to the EPA timer at the same
time that the timer is reset it is indeterminate
which will take precedence Users should not
write to a timer if using EPA signals to reset it
2 VALID TIME MATCHES
The timer must incrementdecrement to the
compare value for a match to occur A match
does not occur if the timer is loaded with a value
equal to an EPA compare value Matches also do
not occur if a timer is reset and 0 is the EPA
compare value
3 P6
PIN4-7 NOT UPDATED IMMEDIATELY
Values written to P6
REG are temporarily held
in a buffer If P6
MODE is cleared the buffer is
loaded into P6
REGx If P6
MODE is set the
value stays in the buffer and is loaded into
P6
REGx when P6
MODEx is cleared Since
reading P6
REG returns the current value in
P6
REG and not the buffer
changes to
P6
REG
cannot
be
read
untilunless
P6
MODEx is cleared
4 WRITE CYCLE DURING RESET
If RESET occurs during a write cycle the con-
tents of the external memory device may be cor-
rupted
5 INDIRECT SHIFT INSTRUCTION
The upper 3 bits of the byte register holding the
shift count are not masked completely If the shift
count register has the value 32 c n where
n e 1 3 5 or 7 the operand will be shifted 32
times This should have resulted in no shift taking
place
6 PORT 4 ADDRESS BEHAVIOR
For bus timing Modes 1 and 2 specified only on
the 87C196KTKS C-step Port 4 does not retain
the address during the data portion of the bus
cycle
Designs using an 8-bit external memory
system in bus Mode 1 or Mode 2 require an ex-
ternal latch on Port 4 to retain the address during
the data portion of the bus cycle Designs using
an 8-bit external memory system in the KR or
KR a 1 Wait
bus timing modes do not require an
external latch
Designs using 16-bit external
memory systems require an external latch on
both Port 3 and Port 4 in all bus timing modes
33
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