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AD9991

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VERTICAL TIMING GENERATION

The AD9991 provides a very ﬂexible solution for generating

vertical CCD timing, and can support multiple CCDs and dif-

ferent system architectures. The 6-phase vertical transfer clocks

V1–V6 are used to shift each line of pixels into the horizontal

output register of the CCD. The AD9991 allows these outputs to

be individually programmed into various readout conﬁgurations

using a four step process.

Figure 15 shows an overview of how the vertical timing is gener-

ated in four steps. First, the individual pulse patterns for V1–V6

are created by using the vertical pattern group registers. Second,

the V-pattern groups are used to build the sequences, where

additional information is added. Third, the readout for an entire

ﬁeld is constructed by dividing the ﬁeld into different regions and

then assigning a sequence to each region. Each ﬁeld can contain

up to seven different regions to accommodate different steps of

the readout such as high speed line shifts and unique vertical line

transfers. Up to six different ﬁelds may be created. Finally, the

Mode register allows the different ﬁelds to be combined into any

order for various readout conﬁgurations.

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 3: USE V-SEQUENCE 0

REGION 4: USE V-SEQUENCE 2

CREATE THE VERTICAL PATTERN GROUPS

(MAXIMUM OF 10 GROUPS).

BUILD THE V-SEQUENCES BY ADDING LINE START

POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES

(MAXIMUM OF 10 V-SEQUENCES).

V-SEQUENCE 0

(VPAT0, 1 REP)

BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS,

AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH

(MAXIMUM OF 7 REGIONS IN EACH FIELD)

(MAXIMUM OF 6 FIELDS).

FIELD 0

FIELD 1

FIELD 2

REGION 2: USE V-SEQUENCE 3

USE THE MODE REGISTER TO CONTROL WHICH FIELDS

ARE USED, AND IN WHAT ORDER

(MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER).

FIELD 0

FIELD 1

FIELD 2

FIELD 3

FIELD 4

FIELD 5

FIELD 1

FIELD 4

FIELD 2

V-SEQUENCE 1

(VPAT9, 2 REP)

V-SEQUENCE 2

(VPAT9, N REP)

VPAT 0

VPAT 9

Figure 15. Summary of Vertical Timing Generation

REV. 0

AD9991 Datasheet(PDF) 16 Page - Analog Devices

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