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AD9991

–31–

6dB–42dB

CCDIN

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

10-BIT

ADC

VGA

DAC

CLAMP LEVEL

VGA GAIN

CDS

INTERNAL

VREF

2V FULL SCALE

PRECISION

TIMING

GENERATION

SHP

SHD

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT

PHASE

V-H

TIMING

GENERATION

SHP SHD

DOUT

PHASE

CLPOB

PBLK

1.0V

2.0V

DOUT

AD9991

Figure 33. Analog Front End Functional Block Diagram

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9991 signal processing chain is shown in Figure 33.

Each processing step is essential in achieving a high quality image

from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to approxi-

mately 1.5 V, to be compatible with the 3 V supply voltage of the

AD9991.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

shown in Figure 7 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and level of the CCD signal, respectively. The placement of

the SHP and SHD sampling edges is determined by the setting

of the SAMPCONTROL register located at address 0x63. Place-

ment of these two clock signals is critical in achieving the best

performance from the CCD.

Variable Gain Ampliﬁer

The VGA stage provides a gain range of 6 dB to 42 dB, program-

mable with 10-bit resolution through the serial digital interface.

The minimum gain of 6 dB is needed to match a 1 V input signal

with the ADC full-scale range of 2 V. When compared to 1 V full-

scale systems, the equivalent gain range is 0 dB to 36 dB.

The VGA gain curve follows a “linear-in-dB” characteristic. The

exact VGA gain can be calculated for any gain register value by

using the equation

Gain (dB) = (0.0351

Code) + 6 dB

where the code range is 0 to 1023.

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Figure 34. VGA Gain Curve

A/D Converter

The AD9991 uses a high performance ADC architecture,

optimized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.5 LSB. The ADC

uses a 2 V input range. See TPC 2 and TPC 3 for typical linearity

and noise performance plots for the AD9991.

REV. 0

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