ADAV400_15 datasheet(32/36 Pages) AD

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ADAV400

Rev. A | Page 32 of 36

RAM MODULO CONTROL REGISTER

The ADAV400 uses a modulo RAM addressing scheme that

allows very efficient coding of filters and other blocks by

automatically incrementing the data RAM pointer at the end of

each sample period. This works well for most audio applications

that involve filtering. However, in some cases auto-incrementing

the data RAM pointer is undesirable—for example, when it is

required to store a word in data RAM and then access it in a

subsequent audio sample period.

For this reason, the data RAM in the ADAV400 can be partitioned

into modulo and nonmodulo blocks by programming the RAM

modulo control register (see Table 30). This register is

programmed with the size of the modulo block required in blocks

of 512 words, with a maximum data RAM size of 20,480 words,

which is the default setting of the register. For example, if the

1024 (2 × 512) words starting from Address 0 to Address 1023,

and the nonmodulo RAM is 19,456 words starting from Address

1024.

This is not currently used in any of the library blocks within the

development tool; however, it is included for maximum flexibility

for custom software development.

SERIAL OUTPUT CONTROL REGISTERS

Dither Enable (Bit 15)

Setting this bit to 1 enables dither on the appropriate channels.

TDM Output Mode (Bit 14)

This bits selects either 8-channel or 16-channel TDM mode.

LRCLK Polarity (Bit 13)

When this bit is set to 0, the left channel data is clocked when

LRCLK is low, and the right channel data is clocked when LRCLK

is high. When this bit is set to 1, this sequence is reversed.

BCLK Polarity (Bit 12)

This bit controls on which edge of the bit clock the output data

is clocked. Data changes on the falling edge of BCLK1 when

this bit is set to 0, and on the rising edge when this bit is set to 1.

Master/Slave (Bit 11)

This bit determines whether the output port is a clock master or

slave. The default setting is slave; on power-up, Pin BCLK1 and

Pin LRCLK1 are set as inputs until this bit is set to 1, at which

time they become clock outputs.

BCLK Frequency (Bits [10:9])

When the serial output port is a master, these bits set the

frequency of the output bit clock, BCLK1.

Frame Sync Frequency (Bits [8:7])

When the output port is a master, these bits set the frequency of

the output word clock on the LRCLK1.

Frame Sync Type (Bit 6)

This bit sets the type of signal on the LRCLK1 pin. When this

bit is set to 0, the signal is a word clock with a 50% duty cycle;

when this bit is set to 1, the signal is a pulse with a duration of

one BCLK at the beginning of the data frame.

TDM Enable (Bit 5)

Setting this bit to 1 changes the output port from multiple serial

outputs to a single TDM output stream available on SDO0. This

bit must be set in both serial output control registers to enable

16-channel TDM on SDO0.

MSB Position (Bits [4:2])

These three bits set the position of the MSB of the data with

respect to the LRCLK edge. The data outputs of the ADAV400

are always MSB first.

Output Word Length (Bits [1:0])

These bits set the word length of the output data-word. All bits

following the LSB are set to 0.

SERIAL INPUT CONTROL REGISTER

TDM Input Mode (Bit 5)

This bit selects either 8-channel or 16-channel TDM mode.

LRCLK Polarity (Bit 4)

When this bit is set to 0, the left channel data on SDINx is

clocked in when LRCLK1 is low, and the right channel input

data is clocked in when LRCLK1 is high. When this bit is set to 1,

this sequence is reversed.

In TDM mode, when this bit is set to 0, data is clocked on the

next valid BCLK edge (polarity of BCLK is set in Bit 3 of this

set to 1 and running in TDM mode, the input data is valid on the

BCLK edge following a rising edge on LRCLK1.

The serial input port can also operate with LRCLK1 as a pulse,

rather than a clock. In this case, the first edge of the pulse is used

by the ADAV400 to start the data frame. When the polarity bit

is set to 0, data is clocked in on the falling edge of LRCLK1; when

this bit is set to 1, data is clocked in on the rising edge.

BCLK Polarity (Bit 3)

This bit controls on which edge of the bit clock the input data

changes and on which edge it is clocked. Data changes on the

falling edge of BCLK1 when this bit is set to 0, and on the rising

edge when this bit is set at 1.

Serial Input Mode (Bits [2:0])

These two bits control the data format that the input port expects

to receive. It should be noted that Bit 3 and Bit 4 of the serial input

control register will override these settings, so Bits 4 to Bit 0

must be set for correct operation. Refer to Figure 31, Figure 32,

Figure 33, and Figure 34 for details on the different modes.

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