ADAV400_15 datasheet(24/36 Pages) AD

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ADAV400

Rev. A | Page 24 of 36

CONTROL PORT READ/WRITE DATA FORMATS

The read/write formats of the control port are designed to be

byte oriented. To conform to this byte-oriented format, 0s are

appended to the data fields before the MSB to extend the data-

word to the next multiple of eight bits. For example, for

parameter RAM, a 28-bit word is appended with four leading

0s, making the transfer four bytes; for program RAM, a 42-bit

word is appended with six leading 0s, making the transfer six

bytes. The data fields are appended to a 3-byte field consisting

of a 7-bit chip address, a read/write bit, and an 11-bit

RAM/register address for full I2C transfer.

Burst mode is used to fill contiguous register or RAM locations.

A burst mode write is initiated by writing the address and data

of the first RAM/register location to be written followed by the

next data-word, and so on. The ADAV400 control port auto-

increments the internal address counter depending on the

location being written to or read from, even across the

boundaries of the different RAMs and registers locations.

Table 16. Parameter RAM Read/Write Format (Single Address)

Byte 0

Byte 1

Byte 2

Byte 3

Bytes [4:6]

chip_adr [6:0], R/W

000, param_adr [12:8]

param_adr [7:0]

0000, param [27:24]

param [23:0]

Table 17. Parameter RAM Block Read/Write Format (Burst Mode)

Byte 0

Byte 1

Byte 2

Byte 3

Bytes [4:6]

Bytes [7:10]

Bytes [11:14]

chip_adr [6:0], R/W

000, param_adr [12:8]

param_adr [7:0]

0000, param [27:24]

param [23:0]

0000 param [27:0]

First parameter (param_adr)

Second parameter

(param_adr + 1)

Third parameter

(param_adr + 2)

Table 18. Program RAM Read/Write Format (Single Address)

Byte 0

Byte 1

Byte 2

Bytes [3:8]

chip_adr [6:0], R/W

000, prog_adr [12:8]

prog_adr [7:0]

prog [42:0]

Table 19. Program RAM Block Read/Write Format (Burst Mode)

Byte 0

Byte 1

Byte 2

Bytes [3:8]

Bytes [9:14]

Bytes [15:20]

chip_adr [6:0], R/W

000, prog_adr [12:8]

prog_adr [7:0]

prog [39:0]

First program word (prog_adr)

Second program word

(prog_adr + 1)

Third program word

(prog_adr + 2)

Table 20. Control Register Read/Write Format (16-Bit Register)

Byte 0

Byte1

Byte 2

Byte 3

Byte 4

chip_adr [6:0], R/W

000, reg_adr [12:8]

reg_adr [7:0]

data [15:8]

data [7:0]

Table 21. Control Register Read/Write Format (8-Bit Register)

Byte 0

Byte1

Byte 2

Byte 3

chip_adr [6:0], R/W

000, reg_adr [12:8]

reg_adr [7:0]

data [7:0]

Table 22. Data Capture Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

chip_adr [6:0], R/W

000, data_capture_adr [12:8]

data_capture_adr [7:0]

000, progCount [10:6]

progCount [5:0], regSel [1:0]

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