ADAV400_15 datasheet(23/36 Pages) AD

23 / 36 page

ADAV400

Rev. A | Page 23 of 36

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

TIME (ms)

The ADAV400 data capture feature allows the data at any node

in the signal processing flow to be sent to one of six registers

that can be read by the control port or to a serial output pin.

Use this feature to monitor and display information about

internal signal levels or compressor/limiter activity.

The ADAV400 contains six independent data capture registers

that can be read via the I2C control port and can be used for

monitoring static signals. In addition, two I2S digital output

capture registers are available for monitoring dynamic signals.

For each of the data capture registers, a capture count and a

between 0 and 2559 that corresponds to the program step

number where the capture will occur (see Table 15).

Figure 30. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale

SAFE LOAD REGISTERS

Table 15. Data Capture Control Registers

Many applications require real-time control of signal processing

parameters, such as filter coefficients, mixer gains, multichannel

virtualizing parameters, or dynamics processing curves.

Function

13:2

12-bit program counter address

1:0

00 = Mult_X_input

For example, if we consider a biquad to prevent instability from

occurring, all five parameters of a biquad filter must be updated

at the same time. Otherwise, the filter may execute with a mix

of old and new coefficients for one or two audio frames. To

eliminate this problem, the ADAV400 uses the safe load registers;

there are five registers for the 28-bit parameter data and five for

the parameter addresses. These addresses will indirectly address

either the parameter RAM or the target/slew RAM.

01 = Mult_Y_input

10 = MAC_output

11 = Accum_fback

The register select field selects which one of four registers

within the DSP core will be transferred to the data capture

The capture count and register select bits are set by writing to

one of the eight data capture registers at the following register

addresses:

Once these registers are loaded, the appropriate initiate safe

transfer bit (there are separate bits for parameter and target/slew

loads) in the audio core control register should be set.

•

4170: Control Port Data Capture Setup Register 0

The last five instructions of the program RAM are used for the

safe load process, so the program length should be limited to

2555 cycles (2560 − 5). It is guaranteed that the safe load occurs

within one LRCLK period (21 μs at fS = 48 kHz) of the initiate

safe transfer bit being set. Safe load only updates those safe load

registers that have been loaded with new data since the last safe

load operation. For example, if only two parameters or target

RAM locations are to be updated, it is only necessary to load

two of the safe load registers; the other safe load registers are

ignored because they contain old data.

•

4171: Control Port Data Capture Setup Register 1

•

4172: Control Port Data Capture Setup Register 2

•

4173: Control Port Data Capture Setup Register 3

•

4174: Control Port Data Capture Setup Register 4

•

4175: Control Port Data Capture Setup Register 5

•

4176: Digital Out Data Capture Setup Register 0

•

4177: Digital Out Data Capture Setup Register 1

The captured data is in 5.19 twos complement data format for

all eight register select fields. The four LSBs are truncated from

the internal 5.23 data-word.

DATA CAPTURE REGISTERS

Data capture registers are used for debugging user-programmed

blocks and are not required when using pre-existing library blocks.

The formats for writing and reading to the data capture

registers are listed in Table 22 and Table 23.

ADAV400 Datasheet(PDF) 23 Page - Analog Devices

ADAV400 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL