UPD16664 datasheet(4/52 Pages) NEC

4 / 52 page

Data Sheet S13780EJ1V0DS00

µµµµ PD16664

3. BLOCK FUNCTION

(1) Address management circuit

This circuit converts addresses from the system via A0 to A16 into addresses corresponding to the memory map

of the internal RAM.

By using this function and four

µ PD16664 modules, addresses for up to 416 × 320 pixels can be managed,

making it easy to construct a liquid crystal display system.

Addresses 1FF00H to 1FF1EH are allocated to a gray level palette register, and any four gray levels can be

selected from a 25-level palette.

(2) Arbiter

This circuit arbitrates conflicts between access by the system to the RAM and reading the RAM by the LCD

driver.

(3) RAM

This is a static RAM of 208 x 160 x 2 bits (single port).

(4) Data bus control

This circuit controls the data transfer direction depending on whether the system reads or writes the RAM of the

µ PD16664.

The data bus width can be changed between 8 and 16 bits by the BMODE pin.

(5) Gray level generation circuit

This circuit offers 25 levels by means of frame interpolation and pulse width modulation.

(6) Internal timing generation

This circuit generates internal timing signals for each block from the /FRM and STB signals.

(7) CR oscillator

This oscillator generates a clock that serves as the reference of the frame frequency in the master mode.

Because this CR oscillator has an on-chip capacitor, the necessary oscillation frequency can be adjusted by using

an external resistor.

Oscillation is stopped in the slave mode.

(a) 1/160 duty

The frame frequency is 1/1296 of the oscillation frequency of this oscillator. For example, when the frame

frequency is 70 Hz, the oscillation frequency is 90.72 kHz.

(b) 1/128 duty

The frame frequency is 1/1040 of the oscillation frequency of this oscillator. For example, when the frame

frequency is 70 Hz, the oscillation frequency is 72.80 kHz.

(8) Liquid crystal timing generation

This circuit generates the /FRM (frame signal), STB(column drive signal strobe), and PULSE (25-level pulse

modulation clock) signals in the master mode.

UPD16664 Datasheet(PDF) 4 Page - NEC