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UM1693 Datasheet(PDF) 53 Page - STMicroelectronics

Part # UM1693
Description  M0-7 standard high-side drivers hardware design guide
PDF  196 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM1693 Datasheet(HTML) 53 Page - STMicroelectronics

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UM1693
Usage/handling of fault reset and standby
195
temperature and high battery voltage, may trigger the power limitation, leading to latch-off of
the HSD. In consequence the load will not be turned on. Even though the device could be
restarted again by toggling FaultRST pin low for a time longer than tLATCH_RST, so that all
latches are reset, the latch will occur again as long as the device is maintained in latch-off
mode.
A possible way to overcome this issue is managing the FaultRST pin in such a way that the
latch-off functionality is blanked out for a time longer than the time of the inrush of the bulb.
The following figure is giving an example, on how the correct turn-on of an incandescent
bulb is ensured by means of a 20 ms blanking pulse on FaultRST pin. Despite the device
toggles in Power Limitation for approximately 10 ms, the load is correctly activated with
negligible delay.
Figure 31. FR handling example - bulb inrush blanking (VNQ7140AJ-E)
Even more, the FaultRST pin can be managed as a global system pin, connecting this pin of
several high-side drivers in parallel to a specific microcontroller I/O port (refer to example in
Figure 32 and Section 8.1: Paralleling of logic input pins for advice on how to parallel pins).
This signal is always kept high, means all connected devices are configured in latch-off
mode, except
•
For a periodical “unlatch” pulse for duration longer than tLATCH_RST max, once per
diagnostic period. This “unlatch” pulse aims at restarting all latched channels, which
are supposed to be restarted, i.e. when the debouncing strategy for short circuit
detection is not yet elapsed.
•
For a blanking pulse (FaultRST low for i.e. 10 ms) generated at every activation of any
channel.
Figure 33 illustrates the described FaultRST pin handling concept.
GAPG1122131113MS
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