UM1693 datasheet(37/196 Pages) STMICROELECTRONICS

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UM1693

Protection against battery transients

195

3.5

Basic application schematic to protect a M0-7 standard

monolithic high-side driver

The hardware design techniques used for an application will establish the baseline immunity

performance. The purpose of hardware techniques is to protect the device from

performance degradation or long-term reliability problems.

Below reported, the STM application proposal, for protecting monolithic HSDs under the

common stress event mentioned ISO 7637-2 editions 2004 and 2011.

To provide these electronic safeguards, manufacturers typically chose either a diode, or

resistor or capacitor for protecting both data-line and supply rails.

Components used to suppress or control transients, as well as their implementation details,

are described in the next paragraph, providing a basic description of how the most typically

used components are employed in low-cost designs for achieving the desired level of

transient immunity.

Components used to suppress or control transients can be grouped into two main

categories:

•

Components that shunt transient currents (voltage limiters)

•

Components that block transient currents (current limiters)

Note that depending on the rise time (frequency bandwidth) of the transient, a component

may function as either a shunt or a block. For instance, at a slow rise time (low frequency

bandwidth) an inductor will have little impedance (a shunt). At faster rise times (higher

frequency bandwidth), an inductor will have greater impedance (a block). As a result,

transient suppression components must be carefully selected for the optimal operating

conditions. The actual performance of the component in the application will depend on the

frequency-based characteristics of the component and the board layout.

Table 6. ISO 7637-2: 2011 (E)

Test

pulse(1)

Selected

test

level(2)

Test pulse severity level,

(3) (4)

Min. number

of pulses or

test times

Burst cycle/pulse repetition

time

III

I/II

Min.

Max.

-150 V

-112 V

-75

500 pulses

0.5 s

(5)

+112 V

+55 V

+37

500 pulses

0.2 s

5 s

+10 V

+10

10 pulses

0.5 s

5 s

-220 V

-165 V

-112

1 h

90 ms

100 ms

+150

+112 V

+75

1 h

90 ms

100 ms

Test pulse as inin 5.6 paragraph of ISO 7637-2:2011(E) (see Appendix A: References).

Values agreed between vehicle manufacturer and equipment supplier.

The amplitudes are the values of US as defined for each test pulse in 5.6 paragraph of ISO 7637-2:2011(E) (see Appendix

A: References).

The former levels I and II are revised because they did ensure sufficient immunity in subsequent road vehicles’ design.

The maximum pulse repetition time shall be chosen such that it is the minimum time for the DUT to be correctly initialized

before the application of the next pulse and shall be

≥ 0.5 s.

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