UM1693 datasheet(30/196 Pages) STMICROELECTRONICS

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Reverse battery protection

UM1693

30/196

DocID025505 Rev 1

Measured values (VND7020AJ-E)

Table 4 reports the measurement results on VND7020AJ-E test vehicle, according to the

schematic in Figure 11: VCC voltage on device is completely decoupled from the reverse

battery voltage. No negative voltage is present on MultiSense and on logic pins. By reverse

polarity, the MOSFET will be switched off, because the gate source voltage for this case will

be positive VGS > 0 (voltage drop over the Zener diode) and protects the HSD.

The same reverse polarity protection network can be shared among several HSD connected

to the battery.

A capacitor might be placed between gate and source of the P-channel MOSFET. The RC

filter composed by R2 and C can be dimensioned to be transparent against the fast negative

pulses ISO 7637-2:2004(E) pulse 1 test level IV, keeping the reverse polarity protection

circuitry switched ON. The usage of such capacitor C is not recommended, when the

system must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it

is needed that the pulse does not discharge through the HSD and the conducting P-channel

MOSFET as this might be destructive for the HSD.

Figure 12. MOSFET solution in VCC – experiment VND7020AJ-E-E, ISOpulse 1

(-100 V, 90

Ω)

Figure 12 shows the example of a 55 V/16 m

Ω P-channel MOSFET in the schematics as

per Figure 11 submitted to ISO 7637:2-2004(E) pulse 1 transients. In order to limit the

Table 4. Static reverse battery - voltages on pins

Reverse battery

(

VBAT = -16 V)

Normal operation

(standby mode)

Normal operation

(out0 = on, out1 = off)

Normal operation

(out0 = on, out1 = on)

VBAT [V]

-16.02

14.02

14.00

13.98

VCC [V]

14.02

13.99

13.97

VG_Q1 [V]

IR2 [µA]

R2 = 1k

Gate capacitance discharging (~11nF)

MOSFET in avalanche

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