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AN4129 Datasheet(PDF) 28 Page - STMicroelectronics

Part # AN4129
Description  STEVAL-ILL044V1: 9 W Triac dimmable, high power factor
PDF  39 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4129 Datasheet(HTML) 28 Page - STMicroelectronics

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Circuit description and design guidance
AN4129
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Doc ID 023314 Rev 1
insignificant for the damping function. So the ringing network primarily consists of the filter
inductor and the converter input capacitor.
The typical damping network across a current-sink load would consist of a capacitor and a
resistor in series. The minimum capacitor value would be 3 times the filter capacitance (3X
C1, use 0.33 µF), and a resistor of:
Equation 10
However, power dissipation in the damping resistor can be a problem. If the dimmer is set to
90 degrees conduction, the input voltage comes on at the peak of the line waveform. The
damping resistor must charge the damping capacitor 120 times a second to the peak line
voltage. For each transient, the energy dissipated in the resistor is slightly less than:
Equation 11
Other damping mechanisms exist, however, so the damping network does not need to be so
large. Reducing the size of the capacitor would allow the use of a 1/2 W resistor.
The PFC-flyback converter, unlike a regulating converter, has a POSITIVE input resistance
near the filter's resonant frequency. The input current it draws increases when the line
voltage increases, short term. This contributes some damping. The effective resistance can
be calculated from line voltage and input power. Input power is about 11 W. At nominal line
the input resistance is:
Equation 12
Note that this resistance rises and falls as the square of the line voltage.
Some additional damping is provided by the winding resistance of the inductors and the
fusible resistor. It was found experimentally that the ringing could be completely damped
with a series R-C network of 0.22 µF and 390
Ω. The final filter design is shown below:
Figure 35.
Final input filter design



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