AN2960 datasheet(11/41 Pages) STMICROELECTRONICS

11 / 41 page

AN2960

Digital interfaces

Doc ID 15557 Rev 1

11/41

4.1.1

I2C operation

The transaction on the bus is started through a START (ST) condition, which is defined as a

HIGH to LOW transition on the data line, while the SCL line is held HIGH. After the START

condition has been generated by the master, the bus is considered busy. The next byte of

data transmitted contains the address of the slave in the first 7 bits and the 8th bit instructs

whether the master is receiving data from the slave or transmitting data to the slave (SAD

subsequence). When an address is sent, each device in the system compares the first

seven bits after a start condition with its own address. If they match, the device considers

itself addressed by the master.

The slave address (SAD) associated with the LIS331DL may be selected from the two

predefined values 0011100b or 0011101b depending on the logic level present on the SDO

pin. Specifically, if the SDO pin is either connected to Vdd_IO or left unconnected, the slave

address is 0011101b. Otherwise, when it is connected to GND, the slave address is

0011100b. When placing two sensors on the same bus is not required, it is recommended to

use slave address 0011101b by either connecting the SDO pin to Vdd_IO, or leaving it

floating.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver that

has been addressed is obligated to generate an acknowledge after each byte of data has

been received.

The I2C embedded in the LIS331DL behaves as a slave device and the following protocol

must be adhered to. After the start condition (ST), a slave address is sent. Once a slave

acknowledge (SAK) has been returned, an 8-bit sub-address will be transmitted: the 7 LSb

represents the actual register address, while the MSB enables address auto-increment. If

the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented

to allow multiple data read/write. Otherwise, if the MSB of the SUB field is ‘0’, the SUB will

remain unchanged and multiple read/write on the same address can be performed.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the master transmits to the slave with unchanged direction.

Transfer when master is writing one byte to slave

Transfer when master is writing multiple bytes to slave:

Transfer when master is receiving (reading) one byte of data from slave:

Master

SAD + W

SUB

DATA

Slave

SAK

Master

SAD + W

SUB

DATA

Slave

SAK

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

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