Synchronous buck converter testing demonstration board

AN4150

10/20

Doc ID 023526 Rev 1

In a Power MOSFET with planar technology, the gate structure is on the device surface,

realized by a planar poly-silicon electrode, a gate oxide layer and the silicon; these three

layers form the “MOS” capacitor. The gate oxide isolates the metal contact and its thickness

is in the range of a few or several hundreds of angstroms. The drain current flows from the

source (n+region), through the conductive channel, in the vertical direction to the drain.

Considering now the trench technology, some relevant differences are immediately visible.

The gate structure is realized by a deeply dug poly-silicon electrode (highly doped), isolated

by a gate oxide layer. The trench depth is one of the most important process parameters,

2 µm). The drain current flows vertically along the trench sidewall towards the drain contact.

Figure 8 shows the same device structures highlighting the geometrical aspects that affect

the Power MOSFET switching performance.

Figure 7.

Device A (left) and device B (right) cross sections

Figure 8.

Device A (left) and device B (right) cross sections with geometrical

details

gate

Al

SOURCE

N+

P-

N- ( drift region

)

N+ ( sub )

DRAIN

Al

SOURCE

N- (drift region

)

N+ ( sub )

DRAIN

P (body )

AM14944v1

gate

Al

SOURCE

N+

P-

N- (dri region)

N+ (sub )

DRAIN

L

Al

SOURCE

N- (dri region)

N+ (sub )

DRAIN

N+

h

L*

P- (body)

AM14945v1