AN4150

Conclusion

Doc ID 023526 Rev 1

17/20

4

Conclusion

Starting from a single-phase synchronous buck converter topology, the impact of silicon

technology on low-side Power MOSFET gate current has been thoroughly analyzed, by

bench tests and Cadence OrCAD Capture simulations. Trench technologies, which are

preferable in high efficiency DC-DC converters due to their very competitive figure of merit

planar ones; this affects the overall device switching performance. This also means different

gate current behavior, with bigger maximum and minimum gate current peaks and longer

rise/fall times.

These different device characteristics should be monitored particularly when application

features (switching frequency, number of paralleled devices, etc.…) are more critical for

switching behavior, making driver-MOSFET matching optimization mandatory.

Two examples can be given to enforce the previous statements. When more FETs are

and discharge a bigger equivalent capacitance to switch on and off the devices. So, to

minimize the gate drive losses, the driver must have special features, in terms of sink/source

current and resistance, particularly when driving trench Power MOSFETs.

Similarly, in hard-switching applications, where larger losses occur during switching

transients, proper driver choice is needed when higher (Cxx/A) Power MOSFETs must be

turned on and off, improving gate current source and sink and reducing the switching losses.